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Schottky barrier SOI-MOSFETs with high-k La2O3/ZrO2 gate dielectrics

机译:具有高k La2O3 / ZrO2栅极电介质的肖特基势垒SOI-MOSFET

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摘要

Schottky barrier SOI-MOSFETs incorporating a La2O3/ZrO2 high-k dielectric stack deposited by atomic layer deposition are investigated. As the La precursor tris(N,N′-diisopropylformamidinato) lanthanum is used. As a mid-gap metal gate electrode TiN capped with W is applied. Processing parameters are optimized to issue a minimal overall thermal budget and an improved device performance. As a result, the overall thermal load was kept as low as 350, 400 or 500 °C. Excellent drive current properties, low interface trap densities of 1.9 × 1011 eV−1 cm−2, a low subthreshold slope of 70-80 mV/decade, and an ION/IOFF current ratio greater than 2 × 106 are obtained.
机译:研究了结合有通过原子层沉积法沉积的La2O3 / ZrO2高k介电叠层的肖特基势垒SOI-MOSFET。作为La前体,使用三(N,N'-二异丙基甲酰胺基)镧。作为中间隙金属栅电极,使用被W覆盖的TiN。优化了工艺参数,以发布最小的整体热预算和改善的器件性能。结果,整体热负荷保持在350、400或500°C的低水平。获得了出色的驱动电流特性,1.9×1011 eV-1 cm-2的低界面陷阱密度,70-80 mV /十倍的低亚阈值斜率以及大于2×106的ION / IOFF电流比。

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